Components in computers and other information processing devices have been greatly improved in performance. For example, the improvement in performance is achieved in memories, processors, and switch large scale integration (LSI) circuits. In order to improve the performance of systems, it is desirable to increase the signal transmission speed between the components or elements, in addition to the improvement of the components in performance. For example, it is desirable to increase the signal transmission rate between memories, such as static random access memories (SRAMs) or dynamic random access memories (DRAMs), and processors in order to improve the performance of the computers. In addition, along with the improvement of the performance of the information processing devices, such as apparatuses for communication infrastructure, it is desirable to increase the data rate in signal transmission and reception inside and outside the apparatuses. In order to meet the demand for the increase in data rate, the data rates of input-output circuits in many integrated circuits are desirably increased from several gigabits per second to several tens of gigabits per second. For example, as of 2012, it is considered that the data rates of about 10 gigabits per second to 30 gigabits per second are desirably achieved in the current high-end servers and the data rates of about 30 gigabits per second to 60 gigabits per second are desirably achieved in next generation machines. The frequency corresponding to a data rate D [bits/s] is called a baud rate fb (=D) and its reciprocal is called a data period T (=1/fb) or one unit interval (1 UI).
It is desirable to achieve high timing accuracy in circuits composing transmission and reception circuits of signals at such high data rates. This is because 1 UI has a very low value of 10 picoseconds (ps) to 20 ps. It is desirable to set the values of timing jitter of clock signals to be supplied to element circuits to values sufficiently lower than the value of 1 UI. In order to reduce the jitter, it is desirable to increase the sizes of transistors and to increase the power consumption.
In order to reduce the jitter while suppressing the power consumption, design approaches to allocate (budgeting) an appropriate amount of jitter to each element circuit are in widespread use. In such a case, certain jitter budget is allocated to each element circuit to design the circuit so that the amount of jitter that occurs is within the value of the jitter budget. It is desirable to evaluate how much jitter each element circuit in the circuits that have been actually designed generates in order to appropriately perform the design based on the jitter budget.
In addition, loop control circuits are known (for example, refer to Japanese Examined Patent Application Publication No. 6-83193). The loop control circuits each include a saw-tooth-wave generating unit that generates a saw tooth wave that is controlled in response to an input signal and that has a period coinciding with the period of the input signal. In a typical loop control circuit, a sample-hold unit samples and holds the saw tooth wave at a peak position to acquire the maximum voltage of the saw tooth wave. A subtracting unit calculates a differential voltage between the maximum voltage and a reference voltage. An integration unit integrates the differential voltage. A control unit controls the inclination of the saw tooth wave on the basis of the output from the integration unit so that the maximum voltage of the saw tooth wave agrees with the reference voltage. The integration unit performs the integration with a certain time shorter than the sampling period in synchronization with the sampling.
Furthermore, gate pulse generation circuits are also known (for example, refer to Japanese Examined Utility Model Registration Application Publication No. 5-4373). A typical gate pulse generation circuit generates a gate pulse to trigger off the gate for extracting a horizontal synchronization signal from a complex video signal that is read out in a time-axis correction circuit in a recording medium playing apparatus. The gate pulse generation circuit generates a slope signal having a certain period. A sample-hold unit samples and holds the slope signal at timing corresponding to the horizontal synchronization signal included in the complex video signal that is read out. The gate pulse generation circuit shifts the output from the sample-hold unit in level by a certain value to generate first and second shift voltages and generates the gate pulse only while the level of the slope signal is within the range of the first and second shift voltages.